1. Field of the Invention
The present invention relates to a serial access memory and a data write/read method applicable thereto.
2. Prior Art
Generally, in a serial access memory of the line access type, when a line address (X-address) is externally applied thereto, the access (i.e. write/read operation) is executed to a word line as specified with that line address. An exemplary arrangement of a prior art serial access memory 1 of the line access type is illustrated in FIG. 11 of the accompanying drawings as a part of this specification.
The prior art serial access memory 1 is provided with a memory cell array 11, a memory control portion 12, an X-address means 13, a Y-address means on the write side (referred to xe2x80x9cwrite Y-address meansxe2x80x9d hereinafter) 14, a Y-address means on the read side (referred to xe2x80x9cread Y-address means) 15, the first transfer means group on the write side (referred to as xe2x80x9cwrite side first transfer means groupxe2x80x9d hereinafter) 16, a register group on the write side (referred to as xe2x80x9cwrite register groupxe2x80x9d hereinafter) 17, the second transfer means group on the write side (referred to as xe2x80x9cwrite side second transfer means groupxe2x80x9d hereinafter) 18, the first transfer means group on the read side (referred to xe2x80x9cread side second transfer means group) 19, a register group on the read side (referred to as xe2x80x9cread register groupxe2x80x9d) 20, the second transfer means group on the read side (referred to as xe2x80x9cread side second transfer means groupxe2x80x9d hereinafter) 21, an input means 22, and an output means 23.
The X-address means 13 is controlled to select one word line from a plurality of word lines WL1 to WLn (n: positive integer) and to put the selected word line in a logical high-level state (referred to as xe2x80x9cH-levelxe2x80x9d hereinafter) by the memory control portion 12.
The memory cell array 11 is made up of a plurality of memory cells MC11 to MCmn (m: positive integer), each of which is arranged at each of intersections made by the plural word lines WL1 to WLn and the plural bit line pairs BL1, /BL1 to BLm, /BLm. Each of the memory cells MC11 to MCmn includes one each of a transistor (not shown) and a capacitor (not shown).
The bit line pairs BL1, /BL1 to BLm, /BLm are respectively connected with corresponding sense amplifiers SA1 to SAm, with which the potential variation appearing on the bit line pairs BL1, /BL1 to BLm, /BLm is amplified.
In the next, there will be describe the structure of an electronic circuit arranged on the write side of the memory cell array 11.
The bit line pairs BL1, /BL1 to BLm, /BLm are connected with the write register group 17 through the write side first transfer means group 16. The write side first transfer means group 16 is made up of a plurality of write side first transfer means 16-1 to 16-m of which each corresponds to each of the bit line pairs BL1, /BL1 to BLm, /BLm. The write register group 17 is made up of a plurality of write registers Wreg-1 to Wreg-m of which each corresponds to each of the bit line pairs BL1, /BL1 to BLm, /BLm.
Each of the write side first transfer means 16-1 to 16-m is made up of two transistors. For instance, the bit line BL1 is connected with the write register Wreg-1 through the drain and source of one transistor forming the write side first transfer means 16-1 while the bit line /BL1 is connected with the write register Wreg-1 through the drain and source of the another transistor forming the write side first transfer means 16-1. The ON/OFF control of these 2xc3x97m transistors forming the write side first transfer means 16-1 to 16-m is carried out with a control signal WT.
The write register group 17 is connected with write data buses WD, /WD through the write side second transfer means group 18. This write side second transfer means group 18 is made up of a plurality of write side second transfer means 18-1 to 18-m, which correspond to the write registers Wreg-1 to Wreg-m making up the write register group 17, respectively.
Each of the write side second transfer means 18-1 to 18-m is made up of two transistors. For instance, the write register Wreg-1 is connected with write data buses WD, /WD through respective drains and sources of two transistors forming the write side second transfer means 18-1. Each of the write side second transfer means 18-1 to 18-m is made up so as to receive the write Y-address signals YW1 to YWm outputted from the write Y-address means 14, and the ON/OFF control of two transistors forming each of the write side second transfer means 18-1 to 18-m is carried out with the write Y-address signals YW1 to YWm.
The write data buses WD, /WD are connected with an input terminal DIN through the input means 22.
In the next, there will be described the structure of an electronic circuit arranged on the read side of the memory cell array 11.
The bit line pairs BL1, /BL1 to BLm, /BLm are connected with the read register group 20 through the read side first transfer means group 19. The read side first transfer means group 19 is made up of a plurality of read side first transfer means 19-1 to 19-m, of which each corresponds to each of the bit line pairs BL1, /BL1 to BLm, /BLm. The read register group 20 is made up of a plurality of read registers Rreg-1 to Rreg-m, of which each corresponds to each of the bit line pairs BL1, /BL1 to BLm, /BLm.
Each of the read side first transfer means 19-1 to 19-m is composed of two transistors. For instance, the bit line BL1 is connected with the read register Rreg-1 through the drain and source of one transistor forming the read side first transfer means 19-1 while the bit line /BL1 is connected with the read register Rreg-1 through the drain and source of the another transistor forming the read side first transfer means 19-1. The ON/OFF control of these 2xc3x97m transistors forming the read side first transfer means 19-1 to 19-m is carried out with a control signal RT.
The read register group 20 is connected with read data buses RD, /RD through the read side second transfer means group 21. This read side second transfer means group 21 is composed of a plurality of read side second transfer means 21-1 to 21-m respectively corresponding to the read registers Rreg-1 to Rreg-m which make up the read register group 20.
Each of the read side second transfer means 21-1 to 21-m is made up of two transistors. For instance, the read register Rreg-1 is connected with read data buses RD, /RD through the respective drains and sources of two transistors forming the read side second transfer means 21-1. Each of the read side second transfer means 21-1 to 21-m is formed so as to receive the read Y-address signals YR1 to YRm outputted from the read Y-address means 15, and the ON/OFF control of two transistors forming each of the read side second transfer means 21-1 to 21-m is carried out with the read Y-address signals YR1 to YRm.
The read data buses RD, /RD are connected with an output terminal DOUT through an output means 23.
The write/read operation of the prior art serial access memory 1 as arranged above will now be described with reference to FIGS. 12 and 13.
FIG. 12 is a timing chart for describing the write operation of the serial access memory 1. The write operation will be described with the passage of time as shown in the figure.
 less than Time t1 greater than  The write operation is commenced when a write X-address WXAD is serially inputted to the memory control portion 12. At this stage, however, in order to make it possible for the memory control portion 12 to take in the write X-address WXAD, a write address enable signal WADE of the H-level is inputted in advance to the memory control portion 12. To begin with, at time t1, the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion 12. After that, each bit data of the write X-address WXAD is taken in sequence in the memory control portion 12 in synchronism with a clock signal CLK.
 less than Time t2 greater than  The least significant bit (LSB) data A1 of the write X-address WXAD is taken in the memory control portion 12, thereby the take-in operation of the write X-address WXAD being completed. At this stage, the write address enable signal WADE to be inputted to the memory control portion 12 is put in the logical low level state (referred to as the L-level herein after). In the following, the description will be made with respect to a case where the word line WL1 is selected with the write X-address WXAD.
 less than Time t3 greater than  The word line WL1 selected at time t2 is put in the H-level by the X-address means 13, and the control signal WT is also put in the H-level by the memory control portion 12. As the result of this, each data stored in the memory cells MC11 to MCm1 connected with the word line WL1 is transferred all at once to the write registers Wreg-1 to Wreg-m through the write side first transfer means group 16. Some bits of the data having been transferred to the write registers Wreg-1 to Wreg-m are masked depending on the contents of the input data DI1 to DIm to be written to the memory cells MC11 to MCm1 (write mask operation). With this, it is attempted to improve the efficiency in the write operation of the input data DI1 to DIm to the memory cells MC11 to MCm1.
 less than Time t4 greater than  The memory control portion 12 detects the write enable signal WE of the H-level in the rise timing of the clock signal CLK. With this, the substantial write operation is commenced. The write Y-address means 14 selects the write Y-address signal YW1 from the write Y-address signals YW1 to YWm and puts it in the H-level. At this time, the input data DI1 inputted from the input terminal DIN has been transmitted to the write data buses WD, /WD through the input means 22. Since the write side second transfer means 18-1 is put in the ON state with the write Y-address signal YW1, the input data DI1 is stored in the write register Wreg-1.
 less than Time t4 to t5 greater than  Up to time t5 from time t4, the write Y-address means 14 selects the write Y-address signals YW2 to YWm in sequence from the write Y-address signals YW1 to YWm in synchronism with the clock signal CLK and puts each of them in the H-level. On one hand, the input data DI2 to DIm are inputted to the input terminal DIN in sequence, and each of the input data DI2 to DIm is stored in the write registers Wreg-2 to Wreg-m.
 less than Time t6 greater than  With the input of a write reset signal WR to the memory control portion 12, there is commenced the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11.
 less than Time t7 greater than  The word line WL1 selected in the period of time t1 through t2 is put in the H-level by the X-address means 13 and further, the control signal WT is put in the H-level by the memory control means 12. As the result of this, the input data DI1 to DIm stored in the write register group 17 are transferred all at once to the memory cells MC11 to MCm1 connected with the word line WL1.
As discussed above, according to the prior art serial access memory 1 of the line access type, it is made possible to execute the write operation on the basis of X-address by X-address (although described about only the word line WL1 here).
FIG. 13 is a timing chart for describing the read operation in connection with the serial access memory 1. The read operation will now be described with the passage of time as shown in the figure.
 less than Time t1 greater than  The read operation is commenced when serially inputting a read X-address RXAD to the memory control portion 12. At this stage, in order to make it possible for the memory control portion 12 to take in the read X-address RXAD, a read address enable signal RADE of the H-level is inputted in advance to the memory control portion 12. To begin with, at time t1, the most significant bit (MSB) data Am of the read X-address RXAD is taken in the memory control portion 12. After that, each bit data of the read X-address RXAD is taken in sequence in the memory control portion 12 in synchronism with a clock signal CLK.
 less than Time t2 greater than  The least significant bit (LSB) data A1 of the read X-address RXAD is taken in the memory control portion 12, thereby the take-in operation of the read X-address RXAD being completed. At this stage, the read address enable signal RADE to be inputted to the memory control portion 12 is put in the L-level. In the following, the description will be made in connection with a case where a word line WL1 has been selected with the read X-address RXAD.
 less than Time t3 greater than  The word line WL1 selected at time t2 is put in the H-level by the X-address means 13, and the control signal RT is also put in the H-level by the memory control portion 12. As the result of this, each data stored in the memory cells MC11 to MCm1 connected with the word line WL1 is transferred all at once to the read registers Rreg-1 to Rreg-m through the read side first transfer means group 19.
 less than Time t4 greater than  The memory control portion 12 detects the read enable signal RE of the H-level in the rise timing of the clock signal CLK. With this, the substantial read operation is commenced. The read Y-address means 15 selects the read Y-address signal YR1 from the read Y-address signals YR1 to YRm and puts it in the H-level. Since the read side second transfer means 21-1 is put in the ON state with the read Y-address signal YR1 of the H-level, the data stored in the read register Rreg-1 is transmitted to the read data buses RD, /RD. The data transmitted to the read data buses RD, /RD is outputted as an output data DO1 from the output terminal DOUT through the output means 23.
 less than Time t4 to t5 greater than  Up to time t5 from time t4, the read Y-address means 15 selects in sequence the read Y-address signals YR2 to YRm from the read Y-address signals YR1 to YRm in synchronism with the clock signal CLK and puts each of them in the H-level. As this goes on, each data stored in the read registers Rreg-2 to Rreg-m is transmitted in sequence to read data buses RD, /RD. Each of data transmitted in sequence to the data buses RD, /RD is outputted as the output data DO2 to DOm from the output terminal DOUT through the output means 23.
As described above, according to the prior art serial access memory 1 of the line access type, it is made possible to execute the read operation on the basis of X-address by X-address (although described about only the word line WL1 here).
By the way, in the write operation of the serial access memory 1 at time t3 shown in FIG. 12, in order to transfer each data stored in the memory cells MC11 to MCm1 to the write registers Wreg-1 to Wreg-m by putting the logical level of the word line WL1 in the H-level, it takes a time of 200 to 300 ns as a write data transfer time. Furthermore, in the read operation of the serial access memory 1 at time t3 shown in FIG. 13, in order to transfer each data stored in the memory cells MC11 to MCm1 to the read registers Rreg-1 to Rreg-m by putting the logical level of the word line WL1 in the H-level, it also takes a time of 200 to 300 ns as a read data transfer time.
In case of the prior art serial access memory 1 of the line access type, since the read operation and the write operation are executed in a synchronism with each other, it is necessary to take account of a case where the write data transfer operation from time t3 in the write operation might overlap with the read data transfer operation from time t3 in the read operation. In addition to this, there might be a case where the self-refresh operation overlap with the above two operations. Therefore, as shown in FIGS. 12 and 13, in the write and read operations of the serial access memory 1, three kinds of time, that is, a write data transfer time, a read data transfer time, and a wait time (period of time t3 through t4, which is about 1.5 xcexcs) which is made by adding a certain margin to the self-refresh time, are set as a functional specification.
As discussed above, in order to commence the substantial data write/read operation of the prior art serial access memory 1, it is needed to wait for the passage of the wait time after one X-address has been applied to the memory control portion 12 and taken in thereby.
In the process of developing or manufacturing the serial access memory 1, there is carried out in general a test in which a predetermined data is first written in each memory cell and then read out therefrom, thereby verifying whether or not each data has been rightly stored in each memory cell without any failure. In case of the serial access memory 1 of the line access type, the above wait time takes place every access to the X-address. Consequently, in the test of the serial access memory 1 in which the write/read operation is carried out with respect to all the X-addresses, this wait time has been a very factor against the reduction of the test time.
The invention has been made in view of the problems as described above and a main object thereof is to provide an improved serial access memory capable of reducing the test time thereof and a data write/read method applicable thereto.
According to the first aspect of the invention, in order to solve such problems as described above, there is provided a data write/read method applicable to a serial access memory of the class in which there are provided a plurality of memory cells arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, the first register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line, and the second register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line. This method is characterized by including the first write step of storing the first input serial data of one word in the first register, and the second write step of transferring the one word data stored in the first register in the first write step, to the plural memory cells connected with each of a plurality of first selected word lines selected from the plural word lines. According to this method, if the first input serial data is stored in the first register only once, the data come to be written in the memory cells connected with plural word lines. Thus, it is made possible to reduce the time required for the data write.
According to the second aspect of the invention, there is provided another data write/read method applicable to the serial access memory. This method further includes the following two steps in addition to the steps of the method according to the first aspect of the invention, that is, the third write step of storing the second input serial data of one word in the first register, the second input serial data of one word being obtained by inverting the logical level of each bit of the first input serial data, and the fourth write step of transferring the one word data stored in the first register in the third write step, to a plurality of memory cells connected with each of a plurality of the second selected word lines selected from the plural word lines. Furthermore, according to the third aspect of the invention, there is provided still another data write/read method applicable to the serial access memory. This method further includes the following steps in addition to the steps of the method according to the first aspect of the invention, that is, the third write step of transferring the data stored in the first register in the first write step, through a logic level inversion and transfer means serving to invert the logical level of the data on the basis of bit by bit, to a plurality of memory cells connected with each of a plurality of the second selected word lines selected from the plural word lines. According to these methods, the one word data stored in the plural memory cells connected with the first selected word line and the one word data stored in the plural memory cells connected with the second selected word line, have such a relation there between that the logical level of each bit of the latter one word data is obtained by inverting the logical level of each corresponding bit of the former one word data.
According to the fourth aspect of the invention, there is provided still another data write/read method applicable to the serial access memory. This method further includes the following two steps in addition to the steps of the method according to the first aspect of the invention, that is, the first read step of selecting two word lines from the plural first selected word lines, transferring the storage data of a plurality of memory cells connected with one of the selected two word lines to the second register, and transferring the storage data of a plurality of memory cells connected with the other word line of the selected two word line to the first register, and the second read step of serially reading out the data transferred to the first register in the first read step and serially reading out the data transferred to the second register. The data write/read method applicable to the serial access memory according to the invention is characterized by including the first read step of selecting one first selected word line from the plural first selected word lines and transferring the data stored in a plurality of memory cells connected with the one first selected word line to the second register, the second read step of selecting one second selected word line from the plural second selected word lines and transferring the storage data of a plurality of memory cells connected with the one second selected word line to the first register, and the third read step of serially reading out the data transferred to the second register according to the first read step and serially reading out the data transferred to the first register according to the second read step. Since the first register and the second register are used when reading the data, it becomes possible to read out the storage data from the memory cells connected with each of two word lines at the same time. The time needed for reading the data can be reduced, accordingly.
Furthermore, the data write/read method applicable to the serial access memory according to the invention includes a step of comparing the data serially read out from the first register with the data serially read out from the second register on the bit by bit basis. According to this method, it is made easier to judge whether or not the data is correctly stored in each memory cell and whether or not the data is rightly read out from each memory cell as well.
Still further, the data write/read method applicable to the serial access memory according to the invention is characterized by including the logical level inversion step of inverting the logical level of each bit of the data which is serially read out from the first register prior to the data comparison step. In case the serial data read out from the first register and the serial data read out from the second register have such a relation there between that the logical level of each bit of the data from the second register is obtained by inverting the logical level of each corresponding bit of the data from the first register, the comparison of the above two data from the first and second registers is made easier if inverting the logical level of each bit of the data from the first register before executing the step of comparison.
According to the fifth aspect of the invention, there is provided a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line and storing input serial data of one word, and a register data transfer means transferring the one word data stored in the register as it is or after inverting the logical level of each bit thereof, to a plurality of memory cells connected with one selected word line selected from the plural word lines. According to the constitution of the serial access memory as described above, it becomes possible to write the data in the memory cells connected with a plurality of word lines when writing and storing an input serial data in the first register only once. Moreover, it becomes possible to selectively store either the data stored in the register or the logical level inverted data stored in the register on the word line by word line basis.
According to the sixth aspect of the invention, there is provided a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having m pieces of a data storage region (referred to as xe2x80x9cm data storage regionsxe2x80x9d hereinafter) and transferring the data stored in m data storage regions, to each of m pieces of memory cell (referred to as xe2x80x9cm memory cellsxe2x80x9d hereinafter) connected with one selected word line selected from the plural word lines, m pieces of a bus data transfer means (referred to as xe2x80x9cm bus data transfer meansxe2x80x9d hereinafter) being assigned to each of m data storage regions and transferring the data transmitted to the data bus to each data storage region, and a bus data transfer instruction means selecting in sequence m bus data transfer means one each or a plurality of them each and instructing the selected bus data transfer means to transfer the data transmitted in sequence to the data buses, to m data storage regions in sequence. With the constitution of the serial access memory as described above, it becomes possible to store the same data in plural storage regions at the same time. Therefore, it become possible to reduce the time needed for storing the data in all the storage regions of the register. It becomes also possible to shorten the length of the data to be transmitted to the data bus as compared with the length of the register.
According to the seventh aspect of the invention, there is provided a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having the m data storage regions and transferring the data stored in the m data storage regions to each of the m memory cells connected with one selected word line selected from the plural word lines, an address means for asserting the m address signals in sequence and outputting the asserted address signals, and the m data transfer means being assigned to each of the m data storage regions and having the function of transferring the m address signals to each of the data storage regions as the data, and also having the function of transferring the input serial data transmitted to the data bus, to each of the m data storage regions with the m address signals. Since the m address signals stored in the data storage regions as the data are asserted in sequence by the address means by one each, the logical level of the data stored in one of the data storage regions comes to be different from that of the data stored in all the other data storage regions in a certain timing, and the address of the data storage region storing the data having the logical level which is different from that of the other data, is shifted every change of the address signal to be asserted. Therefore, the position of the memory cell storing the data having the different logical level is shifted by incrementing the address of the word line selected from the plural word lines by one, every time of asserting the address signal in sequence.